This invention relates to a method of effectively controlling an accumulation type photographic conversion element driven by basic clock signals generated by a central processing unit (CPU) in case of reading out image information of image data in accordance with the mode cycle consisting of the photoelectric conversion, accumulation, transfer, hold and read-out modes.
Recently, in accordance with the development of solid device technique mainly inclusive of an integrated circuit (IC) technique, rapid and large development has also been observed in a technique of an accumulation type photoelectric conversion or transducer element. This technique is, however, not satisfactory for those skilled in this art, and in the field of the application of this art, many techniques or skills have been required, and in order to satisfy these requirements, the image information read-out device is complicated and thus expensive.
FIG. 1 shows a block diagram of a circuit system widely adapted in these days in cases of reading out an image by means of an accumulation type photoelectric conversion element, in which an image sensor 10 consisting of a charge coupled device (CCD) is used as the accumulation type photoelectric conversion element and the image information is synchronized with drive signals CK at an image section 11 to be photoelectrically converted and accumulated (IA), and thereafter transferred (TA) to a hold section 12. The charge once accumulated in the hold section 12 is transferred with a standard scanning system and is then read out (RA) from a read-out register 13 as an image signal PS. The cycle consisting of photoelectric conversion accumulation (IC), transfer (RA) and accumulation read-out (RA) steps is totally equally controlled by the drive signals CK with constant frequencies transmitted from the drive signal generating unit 1, and the timing of this operation is represented by the timing chart shown in FIG. 2. Referring to FIG. 2, in a read-out cycle for an image on a picture image G1, when the photoelectric conversion/accumulation (IA) and the transfer (TA) steps have been completed (at time point t1), the held image information (G1) is read out and the next read-out cycle for the image on a picture image G2 then starts. In the similar manner, when the transfer and hold steps of the image information of the picture image G2 have been completed (at time point t2), the held image information of the picture image G2 is read out and the further next read-out cycle for the picture image G3 starts. Similar operations will be repeatedly carried out in the subsequent steps.
It is necessary for the frequency of the drive signals CK for controlling the respective cycles to be very high such as several hundreds KHz to several MHz for the reason that the application of the drive signals CK with a low frequency makes the accumulating time and the transferring time longer, which adversely results in the degradation of the quality of the image data due to the increasing of the dark current, for example.
Because of this fact, in actual operation, it is necessary to make the frequency of the clock signals CK high and it is also necessary for peripheral circuit elements to have a rapid or quick speed performance or response. These facts make the image information read-out device expensive as a whole. In more detail, the lowering of the frequency of the clock signals CK used as drive signals for the image sensor 10 results not only in a delay of the total processing time, but also the occurrence of a problem of the degradation of the quality such as dark current, for example. On the other hand, the increasing of the frequency thereof to prevent the degradation of the quality, requires the outputting of the image signal at a speed in response to that frequency. This requires a sample-hold circuit to match the image processing system and the processing speed or an analog-to-digital (A/D) converter which is to be operated at high speed, thus being inconvenient.
Taking the above matters into consideration, there has been proposed a driving method with two frequencies in which the frequency of the drive signals CK from the drive signal generating unit 1 is switched in accordance with the magnitude thereof as shown in FIG. 3 so as to thereby utilize the high frequency f1 in the photoelectric conversion/accumulation, transfer and hold modes in the image sensor 10 and to utilize the low frequency f2 only in the read-out mode. In more detail, referring to the timing chart of FIG. 3, with respect to the picture image H1, the photoelectric conversion/accumulation, transfer and hold modes are executed by drive signals of the high frequency f1 and upon the completion of the transfer and hold modes at a time point t10, the read-out mode is started by drive signals of the low frequency f2. During the read-out operation of the picture image H1, the image information of the next picture image HH1 is photoelectrically converted/accumulated, transferred and held, but the accumulated electric charge therefor is based on the low frequency f2, so that the dark current is increased and the quality is also degraded. For this reason, the image information is processed by the high frequency f1 at a time point t11, without utilizing the electric charge, as an image signal P, of the picture image HH1 accumulated during the time when operated with the low frequency f2, to read out the electric charge of the picture image HH1 and then to start the accumulation of an electric charge of the further next picture image H2. The read-out operation of the picture image H2 is performed by the low frequency f2, and the image information of the picture image H2 accumulated at that time is not also utilized as the image signal PS. In the similar manner, the operation continues and the photoelectric conversion/accumulation, transfer, and hold modes are performed by the signal of high frequency f1 and the read-out operation of the accumulated charge is performed by the signal of low frequency f2. During the read-out operation due to the low frequency f2, it is necessary to not use the image data including the dark current component accumulated with the low frequency f2 as the image signal PS. The driving method of the type described above is usually adapted for the read-out process of a stationary picture image, and since it is not necessary for this driving method to be processed at a high speed, integrated circuits and/or other circuit systems can be constructed so as to be operable at a low speed and the output thereof is relatively stable. Against these advantages, the driving method provides disadvantages such as that the processing speed is delayed because the read-out process is carried out by the signal of a low frequency and an extra circuit for switching the frequencies is additionally required.
FIG. 4 is a block diagram showing a drive and read-out system for a conventional image sensor 10 of a generally known type, which is provided with a pulse oscillator 2 for outputting a clock pulse CP with a predetermined frequency. The clock pulse CP is inputted into a control timing unit 3 adapted for controlling the operation and a basic clock 4fcp generated therein is then inputted into a drive timing unit 14 adapted for the driving. The drive timing unit 14 outputs drive signals CK referred to hereinbefore for driving the image sensor 10 in response to the basic clock 4fcp and a vertical synchronizing signal Vsync for representing the synchronism of one picture image scanning due to the operation of the image sensor 10. The whole drive system is totally controlled by a CPU 20, to which a logarithmic converting memory 21 adapted for logarithmic conversion, input/output port 24 and a random access memory (RAM) 25 are operatively connected through a bus line BS. The image signal PS transmitted from the image sensor 10 is inputted into an amplifier 23, from which is transmitted an amplified image signal PSA which is then digitalized (PSD) by an A/D converter 22. The thus digitized value is stored in the RAM 25 as a density value obtained in accordance with a logarithmic table in the converting memory 21. The CPU 20 is also operatively connected to the control timing unit 3 through the input/output port 24, from which a timing signal TM1 controlling the start timing and end timing is outputted and also from which is transmitted a timing signal TM2 which controls the timing of the A/D converter 22, whereby the data conversion from the converting memory 21 can be controlled by the timing signal TM2.
As described in detail hereinbefore, in the driving system for the conventional image sensor 10, the CPU 20 controls or manages the pulse oscillator 2 which always generates pulses with a constant frequency regardless of the operation of the CPU 20. The CPU 20 also controls the driving of the image sensor 10 and the read-out operation of the data. It is thus necessary to use a direct memory access (DMA), which makes the control system complicated, and moreover, in the two-frequency driving method described hereinbefore, the controlling method or operation will be made more complicated.